1. Field of the Invention
This invention relates generally to switched mode power converters and in particular to a regenerative gate drive circuit for voltage control of MOSFETs (Metal Oxide Silicon Field Effect Switching device) and IGBT (Insulated Gate Bipolar Switching device) having means for recovering energy stored in the gate capacitance and means for speeding up gate voltage transitions and reducing output impedance.
2. Description of the Related Art
Losses in the gate drive circuits of switched mode power converters operating in the hundreds of kilohertz and megahertz regions significantly affect their efficiency and complicate thermal design.
As conventional prior art gate drive circuit is shown in FIG. 1 comprising a totem pole pair of field effect switching devices Q1 and Q2 and a gate resistor, Rg. This topology suffers from excessive power dissipation particularly at high frequency. The three major sources of power dissipation are as follows: 1. capacitive energy losses, 2. cross conduction power losses, and 3. linear operation losses.
1. Capacitive energy losses occur during turn-on and turn-off. During turn-on, the gate energy (½CgsVdd2) is stored within the equivalent gate capacitance and the same amount of energy is dissipated in the total series resistance (gate driver resistance Rg and internal gate resistance of the switch Q2). During turn-off, the same energy stored in the gate (½CgsVdd2) is dissipated in the total series resistance. Therefore, the total dissipated power is:Pcapacitive=ƒCgsVdd2 whereƒis switching frequencyCgs is gate-to-source capacitanceVdd is supply voltage
The power is dissipated within the gate circuitry Rg and the internal MOSFET gate resistance. While the energy is independent of the charge and discharge path resistance, this resistance determines the switching times and the current rating of the gate-drive switches.
2. Cross conduction power losses occur when in order to generate narrow pulses, one of the totem pole resistors is turned on before the other one is turned completely off. This mode of operation results in cross conduction losses because both gate drive switching devices conduct simultaneously during switching transitions.
3. Linear operation losses are caused by an overlap of voltage and current across gate drive switching devices during switching transitions.
Another problem of the conventional circuit of FIG. 1 is that the parasitic inductance in series with the gate limits the rate of change in the gate current, and thereby increases the switching time. During switching transients, current flowing through the ‘off’ switch Miller capacitance will go through the gate capacitance as well, turning the device back on, unless an alternative low impedance path is available. In the resistive circuit, this impedance from Zg with the switch Q2 in the on state, where Zg is the total signal and return path impedance from the power supply to the MOSFET's gate.
In a paper by W. A. Tobisz et al, entitled “Zero-Voltage-switched quasi-resonant buck and flyback converters—experimental results at 10 MHz”, Proceedings of IEEE PESC '87 Conference, 1987, pp 404-413, a quasi-resonant gate-drive offers reduced losses at turn-on of the power MOSFET. This circuit does not clamp the gate voltage and may cause an over-voltage, and the gate energy is dissipated within the switch at turn-off.
Circuits described in T. Chen, et al., “A resonant MOSFET gate-driver with complete energy recovery” Proceedings of the 3rd IEEE Power Electronics and Motion Control Conference (IPEMC) 2000, Vol. 1, p. 402-406, and I. D. de Vries, “A resonant power MOSFET/IGBT gate driver”, Applied Power Electronics Conference and Exposition, APEC 2002, vol. 1, pp. 179-185, recover gate energy by reversing the voltage across the resonant inductor once the energy has been transferred to it from the gate capacitance. Topology in Y. Chen, et al. clamps the gate voltage to the source through additional pair of semiconductor devices, but does not provide protection against cross conduction and has low output impedance only during conduction of the clamp diodes. While the gate drive circuit in I. D. de Vries et al, prevents cross conduction, it has high output impedance that makes the MOSFET gate susceptible to false triggering.
In a paper by D. Maksimovic entitled “A MOS gate drive with resonant transitions”, Record of the 22nd IEEE Annual Power Electronics Specialists Conference (PESC), 1991, pp. 527-532, it describes a MOS gate drive circuit that clamps gate voltage to the source and prevents cross conduction during normal operation (excluding operation in the presence of Electromagnetic Pulse of EMP). However, it requires placement of gate drive switching devices close to the MOSFET gate to minimize wiring inductance.
U.S. Pat. No. 5,264,736 issued Nov. 23, 1993 to B. Jacobson discloses a high frequency resonant gate drive for a Power MOSFET. This regenerative topology enables partial energy recovery and protects against cross-conduction. It also provides low output impedance because currents circulate in clamp diodes during the time interval between the gate voltage transitions. However, energy recovery takes place only during the narrow time interval prior to the turn off of the main switching device when voltage across the resonant inductor exceeds the bias supply.
U.S. Pat. No. 6,208,535 issued Mar. 27, 2001 to David Parks discloses a resonant gate driver that provides a resonant switching for a field effect transistor (FET) and associated circuits such as power supplies with synchronous output rectifiers. The resonant switching for a junction FET invokes bipolar mode operation with a diode clamping of the gate, which results in bipolar mode operation without a separate bias power supply. However, this resonant gate driver does not provide energy recovery for efficiency improvement.
In a paper by Patrick Dwane, et al. entitled “An Assessment of Resonant Gate Drive Techniques for use in modem Low Power DC-DC converters” IEEE, Jan. 2005, pp. 1572-1580, various gate drive topologies are reviewed and described including several of the above-identified prior art references.